howto

Organizing legacy projects

Posted Sun, 2010-08-15 18:38 by philippe.faes

This post explains how to import legacy projects into Sigasi HDT. I explain a technique that allows any project organization, even the most chaotic (as legacy projects tend to be) with source files scattered across your hard drive (or drives).

I need to thank Jan-Willem Weijers from IMEC for pointing out this method of work to me.

We will use the Virtual Folders, which were introduced in Eclipse 3.6 "Helios". Using virtual folders, we can organize files into projects, independent of how those files are organized on the hard drive.

Let's assume you have a legacy project with VHDL files in three different libraries. If you're not sure what VHDL libraries are, you probably have only one library: "work".

Creating virtual folders

First, you create a new, empty project. File > New > VHDL Project

Let's suppose that we have three libraries: work, congress and alexandria. If you don't use libraries to organize your VHDL code, just create a virtual folder "work".
For each library you want to use, create a virtual folder with the name of that library. Click New > Folder. Then click Advanced and select Folder is not located on the file system (Virtual Folder). Type the folder name (which corresponds to one of your library names) and press Finish.

Map each virtual folder to a library

In the project explorer, the name of the library is displayed next to each folder. You can see that each folder is still mapped to the work library. We now need to change this mapping, so that each folder is mapped to the correct library.

Open Project > Properties > Libraries. Now remove the old mapping for the work library, and add a new library mapping for each library. Library work maps to project:/work.

Adding the project files

Now comes the fun part. To add files to your newly created virtual folders, you just drag them from your file system to your virtual folder. This works in Windows, in Gnome (Linux) and in Mac OS X. For now, drag and drop does not work from Konqueror (KDE/Linux).

After you drag and drop a file, Eclipse will ask if you want to use a relative file path. For legacy projects, you may want to use absolute path names. In this case, uncheck the box in the Link Files dialog.

You now have a VHDL project that consists entirely of virtual folders and virtual files. You can have several projects that share some or all VHDL files in the most flexible way.

We'd love to hear how you organize your projects. Talk to us in the comments section.

Vertical align

Posted Wed, 2010-02-24 13:49 by philippe.faes

align.mov

Vertical alignment of VHDL code in Sigasi HDT.

The feature demonstrated in this video has been improved. See the new video for the current behavior of vertical align.








How to automatically run the ModelSim Makefile in Sigasi HDT?

Posted Fri, 2010-02-12 16:11 by heeckhau

Sigasi HDT automatically and transparently analyzes your VHDL code in the background while you are designing. Sigasi's objective is to do this as fast as possible to give you real-time feedback. Of course you also still have to simulate your code with a VHDL simulator such as ModelSim. Since a few months, Sigasi HDT can automatically create and update a Makefile to compile your project with ModelSim. And through the use of a builder it is also possible to automatically run this Makefile when you make changes to your design. In this blog post I will explain how.

First verify that vcom and vlib are on your path or add it (export PATH=/opt/altera9.0/modelsim_ase/bin/:$PATH on my machine).

Next make sure that Sigasi HDT creates the Makefile:
Click Window > Preferences > VHDL > Makefiles, enable Mentor Modelsim (vsim) and confirm with OK

The Makefile is generated when you perform a full (re)build of your project. Click Project > Rebuild project to force this build. The Makefile.vsim should appear in the Project Explorer now.

Next you have to add a builder to your project that will automatically execute the Makefile.

Right-click your project (the dlx-project in this example) and select Properties > Builders.

Click New...

Select Program as Configuration Type

Next, configure the builder:

  • Give your builder a name: e.g. ModelSim.
  • Enter "/usr/bin/make" as the location of the program to run.
  • Click Select Workspace to set the Working Directory and select the root of your project (${workspace_loc:/dlx} for my project)
  • Next enter as arguments: --makefile=Makefile.vsim all

With the default settings the ModelSim Makefile will only be run during a manual build or after a "Clean". To make sure Sigas HDT runs make every time you save a changed file, click the build options tab and enable the During auto builds checkbox.

When you close the builder configuration dialog windows, make will automatically be run, and Modelsim's messages will appear in the console view.

Note that warnings and errors in the console are clickable. If you click a message, the corresponding location will automatically be opened in the Editor view.

Hendrik

P.S.: You can add as many extra builders as you want this way. E.g. for extra linting, code generators,...

How to implement "highlight matching brackets" for your custom editor in Eclipse

Posted Thu, 2010-02-11 17:51 by heeckhau

For our VHDL editor view I wanted to implement highlight matching bracket like it exists in JDT. I had to dig a lot longer in the JDT code than anticipated to find out how JDT implements this functionality. As so often is the case in Eclipse development, in the end this turned out to be really easy. It was again a matter of finding with few lines to add...

The key is to override the configureSourceViewerDecorationSupport method from AbstractDecoratedTextEditor in your editor class and call the setMatchingCharacterPainterPreferenceKeys method. Note that the method name contains character and not bracket, which explains why I had to look so hard to find it.

public final static String EDITOR_MATCHING_BRACKETS = "matchingBrackets";
public final static String EDITOR_MATCHING_BRACKETS_COLOR= "matchingBracketsColor";
 
@Override
protected void configureSourceViewerDecorationSupport (SourceViewerDecorationSupport support) {
	super.configureSourceViewerDecorationSupport(support);		
 
	char[] matchChars = {'(', ')', '[', ']'}; //which brackets to match		
	ICharacterPairMatcher matcher = new DefaultCharacterPairMatcher(matchChars ,
			IDocumentExtension3.DEFAULT_PARTITIONING);
	support.setCharacterPairMatcher(matcher);
	support.setMatchingCharacterPainterPreferenceKeys(EDITOR_MATCHING_BRACKETS,EDITOR_MATCHING_BRACKETS_COLOR);
 
	//Enable bracket highlighting in the preference store
	IPreferenceStore store = getPreferenceStore();
	store.setDefault(EDITOR_MATCHING_BRACKETS, true);
	store.setDefault(EDITOR_MATCHING_BRACKETS_COLOR, "128,128,128");
}

Bracket highlighting is configured by two preference keys in a key store: one for enablement and one for the color of the box around the matched bracket. In the above code fragment I forced matching bracket highlighting with store.setDefault(EDITOR_MATCHING_BRACKETS, true); in neutral gray (store.setDefault(EDITOR_MATCHING_BRACKETS_COLOR, "128,128,128");).

I hope this can save you some time,
Hendrik.

How to work with Gaisler's Leon3 SPARC processor

Posted Thu, 2010-02-04 10:46 by philippe.faes

Big projects

During our beta period, some people have had trouble loading very large designs into Sigasi HDT. The processing power required by Sigasi HDT rises with the size of your project, as opposed to the processing power required by a VHDL editor which increases with the size of the file you are editing.

We have been working on improving the responsiveness of Sigasi HDT, and to demonstrate this, I'd like to show you how you use Sigasi HDT to navigate and edit one of the largest open source hardware projects: Gaisler's Leon3 SPARC processor and its accompanying libraries (commonly known as GRLIB). I've downloaded the GRLIB project, and set it up to work with Sigasi HDT. GRLIB uses a lot of different libraries:

libraries in GRLIBlibraries in GRLIB

Still fast

To start off with some performance figures on my computer. I have a standard desktop computer, Core 2 Duo and 2 GiB or RAM. Nothing fancy.
The initial compilation of the full GRLIB project takes 35 seconds on my machine, using a Java heap space of less than 500 MiB. In fact, our upcoming release (due Februari 2010) will knock an extra 40% off that compilation time, bringing it to 20 seconds.

Once Sigasi HDT is started and the project is fully compiled, you move to full speed. If you edit a file an save it, Sigasi HDT will not recompile the full project, but only the small subset that is required to make its internal data structures consistent with your project. This usually takes less than a second.

Try it yourself

Taking a look at other people's code is always a good way to learn. This is especially true for large industrial projects, like GRLIB, rather than hello-world style toy projects. I'd like to thank Jiri and the people from Airoflex Gaisler for sharing this project with the world under the GPL license. (Note that you can purchase a commercial license from Airoflex if you need that.)

To look at GRLIB using Sigasi HDT, you can download a free trial license. After you've started Sigasi HDT, just click "Point to existing project", and you're set to go.

Download the GRLIB project. I've packaged release 1.0.20-b3403, with one actual design and the VHDL libraries that it requires.

What do you think?

I'd love to hear which publicly available VHDL projects you have inspected and learned from. Was it easy to understand them? Were the files well-structured? Did it include documentation or did you have to dive in head first?

Syndicate content