howto

Adding Altera_MF to your project (Cheat Sheet)

I have created a Sigasi (Eclipse) Cheat Sheet to assist you in adding the Altera MegaFunctions (altera_mf) to your Sigasi project.

This Cheat Sheet will be part of the next release. But you can already run it today via:

  1. Click Help > Cheat Sheets..
  2. Click Enter the URL of a cheat sheet and
  3. Enter http://www.sigasi.com/sites/www.sigasi.com/files/AlteraMF.xml
  4. Click OK

This should make it easier to add Altera_MF to your project.

If you spot any typos/errors, let me know.

Hendrik.

Organizing VHDL project: One design in one folder

As discussed in a previous article, you can organize your VHDL files in many ways in Sigasi. The three recommended ways are:

  1. No organization
  2. One design in one folder (described in this article)
  3. Aggregation of reusable projects (coming soon)

This article deals with the "one design – one folder" way of organizing a project. The basic idea is that all of the files for your new hardware design are in one folder on your hard drive.

Adding XilinxCoreLib to your project (Cheat Sheet)

Lots of users are struggling today to add XilinxCoreLib to their project in Sigasi. We plan to make a wizard to make this process easier. But in the mean time I have created a Sigasi (Eclipse) Cheat Sheet to assist you in this process.

This Cheat Sheet will be part of the next release.

Installing translations for Eclipse

Even though Sigasi 2.x does not have internationalisation (it is not translated to any languages other than English), much of Eclipse is in fact translated. If your native language is not English, you might consider installing the Babel language packs

Just select Help > Install new Software, then enter the correct update location for your Eclipse distribution.

How to organize your VHDL hardware projects in Sigasi

The Sigasi development environment allows a very large flexibility on how to organize VHDL projects. So much in fact, that it can become confusing. Let me outline three recommended ways of organizing your VHDL project.

  1. No organization (described in this article)
  2. One design in one folder
  3. Aggregation of reusable projects (coming soon)

In this post, I'll start with the simplest way of organizing: not organizing at all.