Dear Beta user,

With this release we introduce the first real integration with an external tool: ModelSim (vsim). We added an option to automatically generate a Makefile for your project that correctly reflects the real dependencies between design files (in VHDL terms) even if your design consists of multiple VHDL libraries. This results in the shortest recompile times when design files are changed.

We invite you to experiment with this new feature and give us your feedback so we can improve it and extend it to more external tools.

The integration does not stop with generating a solid make file. You can also run make from within Sigasi HDT. The output of vsim will be automatically piped to Sigasi HDT's console view. If vsim reported warnings or errors, these messages are rendered as hyperlinks to easily navigate to the corresponding code in Sigasi HDT (see also this feature request on our forum).

To encourage the use of VHDL libraries to organize your projects. We now clearly mark each VHDL file and folder with the name of the library they belong to.

This release also resolves a lot of reported issues:

• Fixed a bug in our design file dependency analyzer (ticket:59): A direct architecture instantiation now triggers a dependency on the instantiated architecture. This is important if the entity and architecture are not in the same file.
• Fixed a problem with use clauses in declarative parts (ticket:647).
• Provide hovering info for based literals such as 16#11#
  
• VHDL does not allow identifiers that start or end with an underscore, or that contain two consecutive underscores. We improved the way we handle these illegal identifiers. Error markers and messages are much clearer now.
  
• Fixed bug in hierarchy view: double click in hierarchy view failed for external files
• Improved responsiveness of the VHDL context sensitive search.
• Make it more clear when the declare signal quickfix could not guess the datatype:
  The declare signal quickfix guesses the datatype of the undeclared signal. If no good guess can be made, the default value is now __datatype__. Since this is not a valid VHDL identifier, you know that you have to fix it later.

Please let us know what you think about this new release on our user forum.

The Sigasi Team.

P.S.: If you never did an update before, see the FAQ for more information on updates.