1.0 Release

Dear Sigasi HDT user,

We are proud to announce the official 1.0 release of Sigasi HDT, the compelling next-generation development environment for VHDL designers.

Thanks to a lot of valuable comments and feedback trough a very successful public beta program, Sigasi HDT 1.0 has
a relevant and mature feature set:

Intelligent navigation

Navigate to any VHDL object in the design by selecting it in a hierarchical view. Or directly navigate from an object to its declaration.

Instant error reporting

Get immediate feedback on errors introduced by a modification.

Intelligent code completion

Use the tool to assist in completing VHDL constructs based on its knowledge of the design.

Quickfixes

Fix errors by using a quickfix proposed by the tool.

Design Flow Integration

Sigasi HDT allows integration in any toolflow. Automatic Makefile generation for ModelSim is supported out of the box.

Refactoring

Use the tool to make sophisticated code transformations that maintain the behavior of the design.

All these features create a novel user experience that greatly improves productivity.

This release marks the end of the beta program. Please be aware all beta licenses are about to expire. To ensure you are able to continue to use Sigasi HDT, you can purchase a license from our website.

The Sigasi Team.

P.S.: If you never did an update before, see the FAQ for more information on updates.