In this release we present support for the CVS version control system and several other additions and improvements to enhance your VHDL development experience.

Sigasi HDT now has full CVS support. Similar to SVN support, this extension allows you to work with CVS within the Sigasi HDT workbench without having to switch to the command line or to other tools. Remote repository browsing, commit, update, revert,... are all available in a few clicks (More information on how to use the CVS plugin).

Other noteworthy changes:

• Add Sigasi HDT support to general projects (ticket:653): Sigasi HDT only analyzes VHDL code in VHDL projects. If you accidentally selected general project when you created a new project, or imported a project you created with Eclipse, there was no way to enable VHDL support to the project. Therefore we added a Configure > Add Sigasi HDT support item to the project menu.

  

• The VHDL editor in Sigasi HDT now highlights matching brackets. This is very useful when working with vectors. You get immediate visual feedback and never have to count brackets any more.

  

• Improved VHDL analysis speed and decreased memory usage (up to 40% faster).
• Improved generated makefile: the automatically generated ModelSim Makefile (Makefile.vsim) now makes all by default.
• Bugfix in the semantic VHDL analyzer (ticket:714).

Let us know what you think about this new release in the comments or on our forum.

The Sigasi team.

P.S.: If you never did an update before, see the FAQ for more information on updates.