VHDL Blog

I've just finished implementing VHDL protected types, as defined in the VHDL 2000 standard.

As part of our quality assurance process, we run a bunch of VHDL code through our tool. In fact, we've downloaded all freely available VHDL from the internet to stress test our tool. However, none of these projects seem to use protected types. All I can do is run the tests that I have created and compile the VHDL files that one of our users has sent me.

This makes me wonder if the world will ever upgrade from VHDL-93? It has been seventeen years since that standard was approved. Pretty soon, we will start training engineers that were not even born in 1993!

My hypothesis is that engineers won't use more recent standards because EDA companies won't implement them and EDA companies are not interested because their customers don't use the newer standards. The Wikipedia contains a list of simulators with information on which VHDL version is supported. If this list is correct about half of the simulators support VHDL-93. The other half supports VHDL-2002. Never mind VHDL-2008, for which I have the language reference manual lying on my desk. Now I know that Wikipedia might or might not be accurate: if you see any errors in Wikipedia, please update that wiki page.

As an interesting note, the documentation for Xilinx ISim states that their mode for VHDL-200X "provides support for select additional constructs introduced post-VHDL-93." That is exactly what we support: select additional constructs. However, this is a temporary situation. Eventually all EDA providers should strive to support the latest standards in full. What else are standards for? (Which reminds me I should get a copy of Karen Bartleson's book on Effective Standards.)

Anyway, here are two questions for all of you:

1. Which VHDL standard do you use? (and why)
2. If you have any VHDL-2002 or VHDL-2008 lying around that you can share, please do. It would be great for our quality assurance and for proving to the world that recent VHDL standards are useful after all.

   -- Philippe

We shouldn't always be serious. With a good toolkit, VHDL can also be fun.
Although I'm afraid that Sigasi's recovering parser will not be able to recover from following fragment. So you will have to search manually, as in the good old days...

Can you find all words?
architecture, latch, code, register, component, reset, concurrency, sigasi, description, simulation, entity, end, statement, hardware, signal, synthesis, ieee, timing, inout, vhdl

Did you find which word you can form out of the remaining 11 characters?

The most important tasks of digital designers is to write VHDL (or Verilog) code and to verify it. The two tools you need for that are: an editor (or rather: an IDE) and a simulator. Editors are available for free and I've discussed IDE's elsewhere. What concerns me is that there are no high quality open source implementations of a VHDL simulator available.

Now, why is that a concern? I think there are two points to be made.

The first reason why we need an open reference implementation, is more important for me as an EDA tool vendor. We need an open VHDL parser and simulator, so that new players can innovate on VHDL technology. Today, any new company that wants to build a new VHDL tool, needs to write or buy their own parser. The price of a VHDL and Verilog parser from the leading provider is in the order of seven-digits. Not a problem for the top three EDA vendors or the two largest FPGA vendors, but the rest of us will think twice before spending that kind of money. Cheaper reusable parsers and open source parsers are just not good enough to build a commercial product. Universities using these parsers spend all their effort building a prototype that will yield interesting papers, but not a product they can spin off.

The second reason is that hardware designers should be able to choose a high quality low cost simulator. This will enable more people to work with VHDL and with FPGA's. I think the best way to deliver this is through an open source model. I think that other, more complex EDA tools, including synthesizers, require too much of an R&D effort to have them available in an open-source model, so let me focus on simulators. Perhaps we can get to synthesis tools in the next decade.

If there is to be more innovation in EDA, we need a freely available parser and simulator for VHDL, Verilog and SystemVerilog. Contrary to FSF dogma, GPL-style licenses will not provide enough freedom for EDA start up companies. These companies will want to sell their software under a proprietary license model. The least we need is LGPL, but BSD-style would be the best.

In my next post, I will talk about a popular, but not quite good enough VHDL simulator.

Let me know what you think in the comments, or on Twitter.

--
Philippe

Also read my next post.