VHDL Blog

Posts that will make you a better VHDL designer, regardless of the tools you use.

You can easily subscribe to this blog by clicking this rss icon: Syndicate content

How to work with Gaisler's Leon3 SPARC processor

Big projects

During our beta period, some people have had trouble loading very large designs into Sigasi HDT. The processing power required by Sigasi HDT rises with the size of your project, as opposed to the processing power required by a VHDL editor which increases with the size of the file you are editing.

We have been working on improving the responsiveness of Sigasi HDT, and to demonstrate this, I'd like to show you how you use Sigasi HDT to navigate and edit one of the largest open source hardware projects: Gaisler's Leon3 SPARC processor and its accompanying libraries (commonly known as GRLIB). I've downloaded the GRLIB project, and set it up to work with Sigasi HDT. GRLIB uses a lot of different libraries:

libraries in GRLIBlibraries in GRLIB

Still fast

To start off with some performance figures on my computer. I have a standard desktop computer, Core 2 Duo and 2 GiB or RAM. Nothing fancy.
The initial compilation of the full GRLIB project takes 35 seconds on my machine, using a Java heap space of less than 500 MiB. In fact, our upcoming release (due Februari 2010) will knock an extra 40% off that compilation time, bringing it to 20 seconds.

Once Sigasi HDT is started and the project is fully compiled, you move to full speed. If you edit a file an save it, Sigasi HDT will not recompile the full project, but only the small subset that is required to make its internal data structures consistent with your project. This usually takes less than a second.

Try it yourself

Taking a look at other people's code is always a good way to learn. This is especially true for large industrial projects, like GRLIB, rather than hello-world style toy projects. I'd like to thank Jiri and the people from Airoflex Gaisler for sharing this project with the world under the GPL license. (Note that you can purchase a commercial license from Airoflex if you need that.)

To look at GRLIB using Sigasi HDT, you can download a free trial license. After you've started Sigasi HDT, just click "Point to existing project", and you're set to go.

Download the GRLIB project. I've packaged release 1.0.20-b3403, with one actual design and the VHDL libraries that it requires.

What do you think?

I'd love to hear which publicly available VHDL projects you have inspected and learned from. Was it easy to understand them? Were the files well-structured? Did it include documentation or did you have to dive in head first?

Copyright policy of IEEE

Of course our users want to have access to all standard libraries. The most important libraries are std.standard and the IEEE libraries, including std_logic_1164 and std_numeric. A more recent standard is IEEE 1076.2-1996. This standard defines two packages: math_real and math_complex. IEEE does not allow the distribution of the source code of these packages. In order to serve our users, we have packaged the best legal alternative: a preliminary draft of these packages.

Recently, we have noticed some problems with this draft. A user informed of an inconsistency between the draft and the official standard. We knew this was a problem. We had planned to incorporate an official version of the standard in our tool, but it was not on our top-3 priorities. However, when a user posts a problem like this, we assign extra priority points.

So I purchased the official source code of the standard from the IEEE. This standard is protected by copyright law, but I'd like to republish the copyright header of the file, under the principle of fair use:

-- Copyright 1996 by IEEE. All rights reserved. 
-- 
-- This source file is an essential part of IEEE Std 1076.2-1996, IEEE Standard 
-- VHDL Mathematical Packages. This source file may not be copied, sold, or 
-- included with software that is sold without written permission from the IEEE 
-- Standards Department. This source file may be used to implement this standard 
-- and may be distributed in compiled form in any manner so long as the 
-- compiled form does not allow direct decompilation of the original source file. 
-- This source file may be copied for individual use between licensed users. 
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source 
-- file shall indemnify and hold IEEE harmless from any damages or liability 
-- arising out of the use thereof. 

Allow me to paraphrase this:

  1. Don't copy this file unless you pay us.
  2. You can use this file to implement the standard.
  3. But make sure your customers cannot do not see the original file.
  4. Make sure nobody sues us.

I can live with item 1, 2 and 4. IEEE invested money in creating this standard, so they want to safeguard their intellectual property rights. They also want to make sure nobody sues them. I understand. But, unlike their other VHDL standard libraries, they prohibit EDA vendors from redistributing the source code (item 3). That's hard to understand. Especially since the novelty of this particular package is questionable. Because of this copyright restriction, EDA vendors provide only a compiled version of the packages. As a result our users have to guess what's in the standard, because they will not buy a copy from IEEE for $86 plus taxes.

I remember one of my first programming labs in college. The assignment was to provide a set of header files and functions for manipulating complex numbers, including conversion from polar to Cartesian coordinates and vice versa. Basically the same thing I find in IEEE standard for mathematical packages. I would not argue about the relevance of the standard. It is very useful that all VHDL designers can use the same, standardized packages. However, the copyright restrictions seem too far-fetched.

The official version of math_real.vhd contains 593 lines of code. Only 53 of those lines consist of actual VHDL code (i.e. not comments). Similar ratios apply for the math_complex package, adding up to about 150 declarations in total, all of them referring to trivial and well-known mathematical values and definitions (π,2π,π/2 and arctan, sin, arctanh). Again: it's useful that this is standardized, but why do we need to keep the source code of these packages a secret from the general public? We don't do this for all the ANSI-C standard libraries, do we?

I'm sure I'm missing an important point here. Please help me out in the comments.

VRGT8CJXEPGK
XUFVPTR2Y2E2

7-segment display

A few weeks ago, a friend of mine talked about using a seven-segment display in a VHDL lab in his university.

Of course, he wanted his students to simulate before they synthesize. I thought it would be nice to have a module that can emulate a this a seven-segment display as ASCII-art.

7-segment display shows "F62"7-segment display shows "F62"

I created this module in about an hour and after some more minor modifications, I decided to publish it for everybody to use.

Get the most out of VHDL comments

get the most out of VHDL commentsget the most out of VHDL comments

Writing a lot of meaningful comments in your VHDL code is all fine and dandy, but how easy is it to read all those comments? With Sigasi HDT, accessing comments is as easy as hovering your mouse over an identifier.











Why can't VHDL designers live without block selection mode?

One of the most frequently asked questions we get is :"Does Sigasi HDT support block selection (a.k.a. column selection) mode?".
In this blog post I question the need for this feature since there is a more powerful alternative in most use cases.

Syndicate content