Tagged as: InternshipState MachineStatic AnalysisCode Comprehension

Improve State Machine Conditional Analysis

Sigasi develops Sigasi Visual HDL, an Integrated Development Environment (IDE) for digital design in SystemVerilog, Verilog or VHDL. We build this IDE on top of VSCode using their extension API and the Language Server Protocol (LSP). We provide the digital designer with all the facilities that are typically reserved for software developers such as syntax checking, navigation, project management, refactoring and autocompletion.

public boolean canApply(Applicant applicant) {
    var degrees = Set.of("Computer Science", "Informatics", "ICT");
    return (applicant.isBachelor() || applicant.isMaster()) &&
            degrees.contains(applicant.getDegree());
}

Many hardware descriptions use State Machine design patterns to get a grip on the complex state transformations in chips. Because these state machines can get very large and complicated themselves, we offer state machine analysis and visualization to our users.

The current analysis of the branch conditions is rather primitive, and we’d like to address that during this internship. You will investigate labeling each state transition with a complete condition in reduced form. To achieve this, you will have to improve condition discovery by processing the abstract syntax tree of the state machine code, and expand on our symbolic interpreter to reduce the resulting conditions.

architecture RTL of FSM is
    type state is (specification, prototype, code_review, ship);
    signal sigasi_internship : state;
begin
    step : process (clk, rst) is
    begin
        if rst = '1' then
            sigasi_internship <= specification;
        elsif rising_edge(clk) then
            case sigasi_internship is
                when specification =>
                    if uxTeam = '1' then
                        sigasi_internship <= prototype;
                    else
                        sigasi_internship <= specification;
                    end if;
                    
                when prototype =>
                    if featureOwner = "happy" then
                        sigasi_internship <= code_review;
                    else
                        sigasi_internship <= specification; -- back to drawing board
                    end if;
                when code_review =>
                    if reviewer = "LGTM" then
                        sigasi_internship <= ship;
                    end if;
                when ship =>
                    sigasi_internship <= specification; -- next feature
            end case;
            
            
        end if;
    end process step;
    
end architecture RTL;

You will join Sigasi's engineering team and participate in actual product development. You'll be part of the daily scrum. Your code will be a first-class citizen, go through the standard review cycle, and eventually have a tangible impact on our product.

This internship takes place for at least 8 weeks in 2026, at the Sigasi office, near the fascinating city center of Ghent, Belgium. For more information about this internship proposal, e-mail careers@sigasi.com.