Tagged as: InternshipDocumentation

Sigasi Project Evangelist

Sigasi develops Sigasi Visual HDL, an Integrated Development Environment (IDE) for digital design in SystemVerilog, Verilog or VHDL. We build this IDE on top of VSCode using their extension API and the Language Server Protocol (LSP). We provide the digital designer with all the facilities that are typically reserved for software developers such as syntax checking, navigation, project management, refactoring and autocompletion.

To provide accurate analysis, Sigasi needs a project description. This tells us how the source files in a project need to be compiled: which language version to use, what the preprocessor definitions are, etc. Our Classic project format was based on the Eclipse project description. Since we’ve pivoted to VSCode, we’re taking the opportunity to introduce our very own project description, called a Modular Sigasi Project.

• Modular project description
• Classic project description

• JSON

  {
      "targets": {
          "rtl": {
              "command": "vcs -sverilog +incdir+src/ +incdir+user_extension/ -work work src/riscv_signature_pkg.sv src/riscv_instr_pkg.sv",
              "dependencies": [{"UVM": "1.2"}]
          },
          "ml": {
              "directory": ".",
              "libraryMapping": {"target/ml": ["work"]},
              "verilogPreprocessor": {
                  "includeDirectories": ["target/ml/"]
              },
              "dependencies": ["rtl"]
          },
          "test": {
              "command": "vcs -sverilog +incdir+test/ -work test test/riscv_instr_test_pkg.sv",
              "dependencies": [{"UVM": "1.2"}, "rtl"]
          }
      }
  }

• XML

  <?xml version="1.0" encoding="UTF-8"?>
  <projectDescription>
  	<name>internship-example</name>
  	<comment></comment>
  	<projects>
  	</projects>
  	<buildSpec>
  		<buildCommand>
  			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
  			<arguments>
  			</arguments>
  		</buildCommand>
  	</buildSpec>
  	<natures>
  		<nature>com.sigasi.hdt.verilog.ui.verilogNature</nature>
  		<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
  		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
  	</natures>
  	<linkedResources>
  		<link>
  			<name>Common Libraries</name>
  			<type>2</type>
  			<locationURI>virtual:/virtual</locationURI>
  		</link>
  		<link>
  			<name>Common Libraries/IEEE</name>
  			<type>2</type>
  			<locationURI>sigasiresource:/vhdl/2008/IEEE</locationURI>
  		</link>
  		<link>
  			<name>Common Libraries/IEEE Synopsys</name>
  			<type>2</type>
  			<locationURI>sigasiresource:/vhdl/2008/IEEE%20Synopsys</locationURI>
  		</link>
  		<link>
  			<name>Common Libraries/STD</name>
  			<type>2</type>
  			<locationURI>sigasiresource:/vhdl/2008/STD</locationURI>
  		</link>
  	</linkedResources>
  </projectDescription>

To test whether the new modular project description can handle the complexity of real world projects, and to help contributors using our Community Edition, you will configure a number of open source hardware designs with it. The resulting modular project description can be contributed back to the project, if they want it.

This internship takes place for at least 8 weeks in 2026, at the Sigasi office, near the fascinating city center of Ghent, Belgium. For more information about this internship proposal, e-mail careers@sigasi.com.