Sigasi internship proposal 2019-2020
- Skills: Java/Xtend, (System)Verilog (optional)
- Target audience: computer science engineers, electronics engineers, master of informatics
Code formatting has been around for a long time and exists for almost every language imaginable in some shape or form. Yet, after all this time, it still poses issues in about as many languages. There are thousands of edge cases when we talk about formatting, yet a user wants every one of them to be formatted to his liking, either by default or through user configuration.
Verilog and SystemVerilog are computer languages used for the design of digital circuits. These are big and complicated languages, that have a lot of language constructs. To create a formatter for them, we thus need to define at least as many formatting rules that take into account their surrounding context.
If you’ve ever wondered whether to
- use tabs or spaces, this internship will teach you why you should use both
- use C-style or Java-style brackets, this internship will teach you why to allow both
- why a formatter doesn’t do what you want, this internship will show why
The objective of this internship is to extend the current formatter (which only does indentation), and accompanying testsuite, in Sigasi Studio for (System)Verilog such that it formats all the whitespace in a document, not only the indentation.
“The Hardest Program I’ve Ever Written” - Bob Nystrom on dartfmt
This internship takes place in the summer of 2020, at the Sigasi office, close to the city center of Ghent. For more information about this internship proposal, contact email@example.com.