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- Linting
- Verilog linting rules
- Abstract classes cannot be instantiated
- Avoid using general purpose 'always'
- Check header comment
- Combining unary and increment/decrement operators
- Conditionally instantiated design unit not found
- Cyclic class inheritance
- Declaration not found
- Deep nesting of conditional and loop statements
- Deprecated UVM API
- Duplicate signal in sensitivity list
- End name does not match declaration name
- End name not allowed
- End name without begin name
- Function prototype has implicit return type
- Implicit vector to boolean conversion
- Include of globally available declaration
- Incorrect constructor for UVM object or component
- Incorrect override of UVM object
- Incorrect utility macro
- Incorrect UVM object instantiation
- Locally unused port, argument or parameter declaration
- Missing include path in preprocessor configuration
- Mixing statement and block name
- Names differing only by case
- Naming conventions
- Non-blocking assignments are not allowed in functions
- Non-standard assignment patterns
- Non-standard covergroup option
- Non-standard cross item declaration
- Non-standard implicit type conversions
- Order of named declaration list does not match
- Prohibited end of line sequence
- Prohibited macro
- Sigasi support is disabled in this file
- Tool compatibility rules
- Truncation in integer literals
- Type argument value does not match containing class
- Unexpected content following directive
- Unexpected output system task
- Unregistered UVM object
- UVM object name does not match variable name
- UVM phase method does not call superclass method
- Vector as edge event expression
- Verilog ambiguous reference
- Verilog assignment patterns
- Verilog case statements
- Verilog checks on initialization
- Verilog class item visibility
- Verilog coding style
- Verilog duplicate conditions
- Verilog duplicate continuous assignments
- Verilog duplicate declaration
- Verilog duplicate port
- Verilog empty assignment pattern
- Verilog empty concatenation
- Verilog empty parameters
- Verilog empty port
- Verilog empty port in ANSI port list
- Verilog hiding non-virtual methods
- Verilog identifiers and data types
- Verilog implicit net
- Verilog incorrect port declaration
- Verilog inputs
- Verilog out-of-bound method declarations
- Verilog overridden method signatures
- Verilog parameters
- Verilog port and parameter associations
- Verilog processes
- Verilog reg and logic datatype
- Verilog type checking
- Verilog unused declaration
- Verilog unused macros
- Verilog upward reference
- VHDL linting rules
- Bitstring contains non-std_logic metavalue
- Capitalization of identifiers
- Case alternative contains duplicate choices
- Check for component/entity mismatch
- Check header comment
- Clock signal not used as clock
- Comparison of vectors with different sizes
- Dead code linting rule
- Declaration not found
- Deep nesting of conditional and loop statements
- Deprecated IEEE packages and non-standard packages
- Duplicate design units
- Encrypted file is used
- Filename contains primary unit name
- Illegal mode view element mode
- Incomplete port maps and generic maps
- Incomplete reset branch
- Inconsistent clock edge usage
- Inconsistent reset style
- Incorrect vector range direction
- Language feature restrictions
- Library is not available
- Linting rules for arrays
- Linting rules for deferred constants
- Linting rules for design unit locations
- Linting rules for instances
- Linting rules for loops
- Missing label
- Missing mode for record element in mode view
- Multiple objects in one declaration
- Naming conventions
- None or multiple matching entities for component
- Null or empty range
- Order of associations
- Positional association in instantiations
- Prohibited end of line sequence
- Redundant "others"
- Sensitivity list
- Sigasi support is disabled in this file
- Signal or variable is never read
- Signal or variable is never written
- Space before the physical unit
- Superfluous library clause
- Superfluous reset
- Tabs are used
- Testing equality of booleans to true or false
- Types in expressions
- Unbound component instantiation
- Unconstrained signal or variable of integer type
- Unexpected clock edge specification
- Unexpected FSM state type
- Unexpected keyword capitalization
- Vector width in assignments and port maps
- Verilog keywords in VHDL
- VHDL coding style rules
- VHDL language version
- Functional safety
- Rule configuration
- Verilog linting rules
- Rename
- Code lenses
- Visualizing your design
- Inspecting your design
- Verifying your design
- Configuring Sigasi
- Automation
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- Getting help