Sigasi offers Smart Indentation for both Verilog and VHDL. When enabled, the indentation level is automatically adjusted based on the context and the code being written.
When you press enter, Sigasi automatically adjusts the indentation of the current and the next line. Depending on the content of the preceding
line, Sigasi will automatically increase or decrease the indentation level. For example, it may add an extra indent after a module or an entity and remove an indent for the matching endmodule or end entity.
Smart Indentation can be toggled by setting the
Note that the used indentation is based on the indentation and whitespace settings.