Formatting

Automated consistent code formatting makes code more readable and understandable for developers, both when working on their own code and when they’re cooperating with colleagues. To format your code using Sigasi, right-click in the editor and select Format Document. For Verilog, only indentation is applied. For VHDL, Sigasi’s advanced formatter handles indentation, spacing between keywords and references, vertically aligning symbols like <=, keyword casing, and comment alignment. All of these are configurable. Formatting can be applied when saving a file by enabling the editor.formatOnSave setting.

Sigasi’s formatter is context-based and tries to respect the author’s style. So depending on your source style, the formatter will make different choices.

For example, Sigasi decides whether to format a conditional signal assignment on one or multiple lines based on the position of the first else keyword. If you put the else keyword on the first line, the formatter will keep everything on one line. If you put the else keyword on a new line, the formatter will use multiple lines for the assignment.

demo <= (others => '0') when enable = '1'
   else (others => '1') when input  = '1' -- else on new line
   else (others => 'X');

When your source file contains syntactical errors, the formatter cannot accurately figure out the appropriate formatting. For this reason, the formatter is programmed to stop applying whitespace changes beyond syntax errors.

Formatter selection

You likely have many VS Code extensions installed. Any extension can contribute support for any language, including formatting for VHDL and Verilog. To ensure you’re using Sigasi’s formatter, execute the Format Document With… command in the command palette ( Ctrl+Shift+P ) and check that you see (default) to the right of VHDL & SystemVerilog IDE by Sigasi . If it’s not set, select Configure Default Formatter... and then select VHDL & SystemVerilog IDE by Sigasi .

Configuring the formatter

The formatting whitespace, as well as the regions in which it operates, can be configured. Additionally, there are VHDL-specific configarutions to be tuned.

Disable formatting in defined regions

You can disable the formatter for defined regions in your VHDL source files by adding off and on tags:

• off tag: -- @formatter:off
  • Turns off the formatter until the end of the file or until an on tag is encountered
• on tag: -- @formatter:on
  • Reenables the formatter following an off tag

Indentation and whitespace

You can further configure the inserted indentation through the following settings:

• editor.indentSize : Configures the size of the inserted indentation.
• editor.insertSpaces : Ensures Sigasi inserts spaces rather than tabs.
• editor.detectIndentation : Dynamically adjusts the previous two settings based on the indentation style used in the current file.

To instead edit the settings for 1 file only, access the Tab Size & Spaces configuration at the bottom-right of the VS Code window.

If you click Tab Size or Spaces, a dialog box appears at the top-middle of the window.

The options in this menu are only valid for the file in the editor. Before using these actions, ensure your file has been saved.

VHDL formatting configuration

In VHDL, the following properties can be configured:

• Preserve newlines
• Use vertical alignment
• Lowercase/Uppercase keywords
• Alignment column for trailing comments

Refer to the configuration page for all the details.