Rule configuration

The Sigasi linter has reasonable defaults for the configuration of reported problems, but the severity level of certain linting rules is configurable for additional flexibility. Furthermore, some linting rules, such as the VHDL maximum line width rule, are parameterized and can be tweaked to your preference. The documentation page of each specific rule details the configurable parameters.

UI configuration

Linting rules can be configured per project, folder, or file by right-clicking a project, folder, or file in the Projects view, selecting Configure > [Project/Folder/File] Settings, and clicking Verilog Errors/Warnings or VHDL Errors/Warnings.

By now selecting a linting rule, you can change the linting rule’s severity and parameters.

Can’t find the linting rule? Simply hit Ctrl+F and search for it, or use the Quick Fix on the linting violation.

For each VHDL linting rule, you can set the severity of non-conformities per code classification:

Verilog linting rules do not make this distinction.

To open the documentation page of a linting rule, press the icon ➌.

Suppressing problems

You can suppress problems in your code by adding a @suppress comment (-- @suppress for VHDL and // @suppress for Verilog) at the end of the line of the problem. Only configurable issues can be suppressed. If you encounter syntax issues that you’d like to suppress, please contact us .

You can limit the suppression to a specific problem by adding a prefix of the problem message between quotes after @suppress. Sigasi also recommends adding a reason why the problem was suppressed by adding an extra comment after @suppress. Typically, you can simply use the Quick Fix to add the suppressing comment.

<line with problem> // @suppress "Problem message prefix" Reason why problem is suppressed

Manual configuration

We discourage manual configuration—especially for rule parameters besides severity—because it’s easy to get the syntax wrong. The UI should normally suffice for your needs.

To manually configure rules, you need to edit the .settings/com.sigasi.hdt.verilog.linting.prefs and .settings/com.sigasi.hdt.vhdl.linting.prefs files.

To configure the severity of rules, add a line using this template:

${rule id}/severity/${path}={error|warning|info|ignore}

To configure a parameter of a rule, add a line using this template:

${rule id}/params/${parameter}/${path}=${value}

• Where ${rule id} can be the number of the rule (e.g., 140) or all to specify settings for all rule IDs at once. Rule IDs can be found by selecting the rule in the Errors/Warnings settings page. The ID will show up next to the title in the right panel. They are also included in the list of VHDL linting rules and the list of Verilog linting rules. While many rules exist in both languages, they do not have the same ID.
• Where ${path} can be <project> (literally, with brackets!) to set the severity of the entire project, /path/to/folder to set the severity of an entire folder, or /path/to/file.vhd to set the severity of a specific file.

For example, to configure the VHDL maximum line width rule as an error (instead of a warning) parameterized at 80 characters, use the following configuration:

120/severity/<project>=error
120/params/max_line_length/<project>=120

The names of parameters, as well as their valid values, are documented on the individual linting rule pages. They are described using the following notation:

ENTITY   PACKAGE

a’       tab     a’‘quote