Rule configuration

The Sigasi linter has reasonable defaults for the configuration of reported problems, but the severity level of certain linting rules is configurable for additional flexibility. Furthermore, some linting rules, such as the VHDL maximum line width rule, are parameterized and can be tweaked to your preference. The documentation page of each specific rule details the configurable parameters.

UI configuration

Linting rules can be configured per project, folder, or file by right-clicking a project, folder, or file in the Projects view, selecting Configure > [Project/Folder/File] Settings, and clicking Verilog Errors/Warnings or VHDL Errors/Warnings.

By now selecting a linting rule, you can change the linting rule’s severity and parameters.

Can’t find the linting rule? Simply hit Ctrl+F and search for it, or use the Quick Fix on the linting violation.

For each VHDL linting rule, you can set the severity of non-conformities per code classification:

Verilog linting rules do not make this distinction.

To open the documentation page of a linting rule, press the icon ➌.

Suppressing problems

You can suppress problems in your code by adding a @suppress comment (-- @suppress for VHDL and // @suppress for Verilog) at the end of the line of the problem. Only configurable issues can be suppressed. If you encounter syntax issues that you’d like to suppress, please contact us .

You can limit the suppression to a specific problem by adding a prefix of the problem message between quotes after @suppress. Sigasi also recommends adding a reason why the problem was suppressed by adding an extra comment after @suppress. Typically, you can simply use the Quick Fix to add the suppressing comment.

<line with problem> // @suppress "Problem message prefix" Reason why problem is suppressed

Manual configuration

The format depends on the type of project. Modular Projects store their configuration in a .sigasi/settings.json file, while Classic Projects use .prefs files in a .settings directory.

In the templates below, the following placeholders appear:

• ${lang} is either vhdl or verilog (the latter covers both Verilog and SystemVerilog).
• ${rule id} is the number of the rule (e.g., 97), or all to apply the setting to every rule. Rule IDs are shown in the Errors/Warnings settings page in the right panel of each rule, and are also listed in the VHDL linting rules and Verilog/SystemVerilog linting rules overviews.
• ${parameter} is the name of a configurable parameter for the rule. Parameter names and their valid values are documented on the individual linting rule pages.
• ${value} is the value to assign to the parameter. See Parameter value notation below.
• ${path} (Classic Projects only) is the scope of the setting. See Classic Projects below for the exact syntax.

Modular Projects

In the .sigasi/settings.json file, configure the severity of a rule with a key matching this template:

"${lang}.rules.${rule id}.severity": "{ERROR|WARNING|INFO|IGNORE}"

To configure a parameter of a rule, use a key matching this template:

"${lang}.rules.${rule id}.parameters.${parameter}": ${value}

By default, entries placed at the top level of settings.json apply project-wide. To scope them to a specific folder or file, nest them inside an @override block keyed by the path (relative to the project root); to scope them to a specific target, nest them inside an @targets block keyed by the target name. For example, to configure the “line is too long” rule (id 97) for VHDL:

{
    // Applies to the entire project
    "vhdl.rules.97.severity": "WARNING",
    "vhdl.rules.97.parameters.max_line_length": 120,

    "@override": {
        // Applies only to files under src/legacy/
        "src/legacy/": {
            "vhdl.rules.97.severity": "IGNORE"
        }
    },

    "@targets": {
        // Applies only to files in the "synthesis" target
        "synthesis": {
            "vhdl.rules.97.severity": "ERROR"
        }
    }
}

Classic Projects

We discourage manual configuration—especially for rule parameters besides severity—because it’s easy to get the syntax wrong. The UI should normally suffice for your needs.

VHDL rules are configured in .settings/com.sigasi.hdt.vhdl.linting.prefs, and Verilog/SystemVerilog rules in .settings/com.sigasi.hdt.verilog.linting.prefs. In the appropriate file, configure the severity of a rule with a line matching this template:

${rule id}/severity/${path}={error|warning|info|ignore}

To configure a parameter of a rule, add a line matching this template:

${rule id}/params/${parameter}/${path}=${value}

Replace ${path} with <project> (literally, with brackets!) to scope the setting to the entire project, /path/to/folder to scope it to a folder, or /path/to/file.vhd to scope it to a specific file.

For example, to configure the VHDL maximum line width rule as an error (instead of a warning) parameterized at 80 characters, use the following configuration:

120/severity/<project>=error
120/params/max_line_length/<project>=120

Parameter value notation

The valid values for the parameters are documented on the individual linting rule pages. They are described using the following notation:

ENTITY   PACKAGE

a’       tab     a’‘quote