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Licensing of Verilog linting rules

Configurable designer edition linting rules

Designer Edition linting rules are available for all editions.

DescriptionID
Empty loops and conditional branches1
Check naming conventions2
Disallow reg datatype3
Named and positional port connections cannot be mixed5
The packed keyword is required in packed structs and unions6
The module name is a keyword in VHDL and may cause problems in mixed language projects7
Case statement does not cover all cases8
The for loop statement misses mandatory part (Verilog)9
Function prototype has implicit return type10
Parameter port list cannot be empty11
No semicolon expected at this point (Verilog)12
Verilog disallows empty assignments of ordered parameters (Verilog)13
Implicit subprogram port direction14
Default clause has to be the last item in a case statement15
Case statement has multiple default clauses, but only one default clause is allowed16
File name does not match design unit17
File contains multiple design units18
Parameters must have a default value19
Verilog code line too long20
Tabs are not allowed21
File header comment does not match required pattern22
Named port connections have to be used for all instances with many ports24
Named and positional parameter overrides cannot be mixed25
Named parameter overrides have to be used for all instantiations with many parameters26
No event control at the top of always construct27
Default member must be last in assignment pattern28
Only one default member expression is allowed per assignment pattern29
Overwritten type key in assignment pattern30
Duplicate member key in structure assignment pattern31
Mixed named and ordered notation in assignment pattern32
Only variable output ports can have a default value in non-ANSI notation33
Only input or variable output ports can have a default value in ANSI notation34
Register initialization in declarations35
Duplicate formal item within the instantiated unit37
Missing actuals for formals that have no default value38
Excessive number of actuals in ordered notation39
Default clause missing from case statement40
Non-blocking assignments are not allowed in functions41
Consecutive underscores in unit / port identifier42
Underscores at end of unit / port identifier43
Report encrypted regions44
Timing controls are not allowed in functions46
Multiple statements per line47
Missing bit width for parameters wider than 32 bits48
Net data types must be 4-state50
Net data types integral51
Empty parameters53, 54
Invalid package item55
Named connections are not allowed with blank ports56
Unexpected preprocessor directive inside design elements57
Non-packed member in packed structure59
Illegal type in untagged union60
Illegal class member access61
Overridden method signature mismatch62-68
Local parameter has to be initialized69
Local parameter cannot be overridden70
Declaration not found71
Attempted implicit declaration with default nettype none73
Invalid enumeration element range format74
Range of enumeration element is too large75
Invalid construct76
Invalid randomize argument77
Type checking78, 79, 94, 100, 131
Constraint class scope missing80
Constraint class with packed dimensions81
Out-of-bound method signature mismatch82-92
Ambiguous reference93
Duplicate declaration95
Invalid UDP initial value96
Implicit net97
Duplicate conditions98
Upward reference99
Duplicate continuous assignments101
Different file encoding for including file and included file102
Missing macro identifier103
Undefined macro104
Forbidden macro identifier105
Missing `endif106
Missing identifier following expansion107
Failed include108
Macro expansion depth limit reached109
Inclusion loop110
Issues found while expanding macro111
Missing macro argument list112
Mismatched number of arguments113
Unexpected directive operand114
Identifier expansion with an invalid sequence of tokens115
Unexpected conditional compiler directive116
Whitespace following a backtick117
Unknown time literal118
Unexpected operand119
Missing operand120
Invalid preprocessor syntax121
Unsupported include path122
Syntax error123, 124
Invalid macro argument list125
Unbalanced expression126
Unbalanced directive invocation127
Unused macros128
Prohibited macro129
Unused declaration130
Hidden non-virtual methods132
Unexpected empty concatenation133
Unexpected empty assignment pattern134
Incorrect port declaration135-139
Duplicate port140
Empty port in ANSI port list141
Empty port142
Vector as edge event expression143
Implicit vector to boolean conversion144
Missing include path in preprocessor configuration155
Unexpected content following directive156
End name does not match declaration name158
End name not allowed159
Duplicate signal in sensitivity list160
Cyclic class inheritance162
Order of named declaration list does not match163
End name without begin name164
Mixing statement and block name165
Names differing only by case166
Deep nesting of conditional and loop statements167
Include of globally available declaration168
Locally unused port, argument or parameter declaration169
Avoid using general purpose ‘always’170
Non-blocking assignments in functions171
Prohibited end of line sequence172
Non-standard streaming concatenation conversion173
Sigasi support is disabled in this file174
Combining unary and increment/decrement operators175
Non-standard conversion from integral to enum176
Conditionally instantiated design unit not found177
Declaration not found in scope178
Invalid digits in integer literals179
Invalid meta values in decimal integer literals180
Number literal cannot consist solely of underscores181
Truncation in integer literals182
Non-standard cross item declaration183
Non-standard covergroup option184
Non-standard assignment patterns186

UVM linting rules

You need to explicitly enable UVM linting.

DescriptionID
Unregistered UVM object145
Incorrect utility macro146
Type argument value does not match containing class147
Incorrect UVM object instantiation148
UVM object name does not match variable name149
Unexpected output system task150
Incorrect override of UVM object151
Deprecated UVM API152
UVM phase method does not call superclass method153
Incorrect constructor for UVM object or component154

Deprecated linting rules

Deprecated linting rules were used by Sigasi at some point, but they’ve been removed or superseded in the most recent version.

DescriptionReasonID
A Verilog net type keyword cannot be followed directly by the reg keywordSuperseded by a syntax error4
Formal item not found within the instantiated unitSuperseded by a syntax error36
Unexpected trailing , in parameter listSuperseded by the Empty parameters rule (rule 53)52
Regular expressions (RE2/J) compatibility checkSuperseded by checks in the settings58
Ambiguous design unit referenceSuperseded by the more general Ambiguous reference (rule 93)72