Naming conventions

See this page for the VHDL equivalent

Naming Conventions allow you to configure patterns to check the correct naming of your identifiers. You can set two patterns for an identifier: a valid pattern that the identifier name must match and an invalid pattern that it must not match. An identifier name is invalid if it matches both patterns or fails to match the valid pattern. Patterns are configured using regex syntax .

Only names with a specified pattern are checked. Empty patterns are omitted.

Example: To enforce a style where all variables have a _v suffix and don’t contain numbers, you would specify .*_v for the valid pattern and .*[0-9].* for the invalid pattern in the Variable name field.

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "verilog.rules.2.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.2.parameters.class_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.comment_header": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.macro_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.instantiation": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.interface_class_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.interface_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.module_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.package_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.program_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.subprogram_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.function_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.task_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.port_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.input_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.output_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.inout_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.parameter_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.parameter_type_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.struct_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.union_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.net_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.var_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.ud_nettype_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.typedef_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.enum_typedef_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.enum_member_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.generate_block_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.fsm_state_name": { "valid": "${regex}", "invalid": "${regex}" },
    "verilog.rules.2.parameters.constraint_name": { "valid": "${regex}", "invalid": "${regex}" }
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
2/severity/${path}={error|warning|info|ignore}
2/params/class_name/${path}=${regex}	${regex}
2/params/comment_header/${path}=${regex}	${regex}
2/params/macro_name/${path}=${regex}	${regex}
2/params/instantiation/${path}=${regex}	${regex}
2/params/interface_class_name/${path}=${regex}	${regex}
2/params/interface_name/${path}=${regex}	${regex}
2/params/module_name/${path}=${regex}	${regex}
2/params/package_name/${path}=${regex}	${regex}
2/params/program_name/${path}=${regex}	${regex}
2/params/subprogram_name/${path}=${regex}	${regex}
2/params/function_name/${path}=${regex}	${regex}
2/params/task_name/${path}=${regex}	${regex}
2/params/port_name/${path}=${regex}	${regex}
2/params/input_name/${path}=${regex}	${regex}
2/params/output_name/${path}=${regex}	${regex}
2/params/inout_name/${path}=${regex}	${regex}
2/params/parameter_name/${path}=${regex}	${regex}
2/params/parameter_type_name/${path}=${regex}	${regex}
2/params/struct_name/${path}=${regex}	${regex}
2/params/union_name/${path}=${regex}	${regex}
2/params/net_name/${path}=${regex}	${regex}
2/params/var_name/${path}=${regex}	${regex}
2/params/ud_nettype_name/${path}=${regex}	${regex}
2/params/typedef_name/${path}=${regex}	${regex}
2/params/enum_typedef_name/${path}=${regex}	${regex}
2/params/enum_member_name/${path}=${regex}	${regex}
2/params/generate_block_name/${path}=${regex}	${regex}
2/params/fsm_state_name/${path}=${regex}	${regex}
2/params/constraint_name/${path}=${regex}	${regex}