Conditionally instantiated design unit not found

When working on a specific design configuration, designers often exclude design units that are not used in that configuration. However, Sigasi verifies all conditional generate branches. If a disabled branch instantiates a design unit missing from the library, it reports a warning. You can change the severity of this rule or disable it completely if you don’t want to add all potential design units to Sigasi.

VERILOG
module top#(bit InclUART = 1);
    if (InclUART) begin : gen_uart
       // ...
    end else begin
        missing_mock_uart i_mock_uart (.*);
    end
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.177.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
177/severity/${path}={error|warning|info|ignore}
```