Prohibited end of line sequence

When using both Linux and Windows for design development, it’s easy to end up with files that have different end of line sequences:

CRLF in HDL files created on Windows
LF in HDL files created on Linux

You can change the configuration of this rule to enforce a style throughout your Verilog code base. A similar rule exists for VHDL files as well.

Whenever Sigasi detects a file with line endings that are not allowed by this rule, a corresponding issue is reported. Sigasi also provides a Quick Fix to change end of line sequences in this file, or in all Verilog files in the project.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.172.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.172.parameters.allowed_sequences": "{CRLF_AND_LF|CRLF_ONLY|LF_ONLY}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
172/severity/${path}={error|warning|info|ignore}
172/params/allowed_sequences/${path}={CRLF_AND_LF|CRLF_ONLY|LF_ONLY}
```