Verilog ambiguous reference

In Verilog, it is possible to reference identifiers from different files. However, if multiple files are declaring the same identifier, there is no way to know which one should be used. Such cases will be marked as ambiguous references (rule 93). If you’re using Modular Projects and the identifier is contributed by multiple targets, the message will mention the relevant targets to help you debug your project configuration.

You may see these warnings if your project defines multiple design units mapped to the same library. More information about library mappings can be found here.

VERILOG
module inner;
    ...
endmodule

VERILOG
module inner(input x, y);
    ...
endmodule

VERILOG
module bad_code;
    inner inner_inst();
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.93.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
93/severity/${path}={error|warning|info|ignore}
```