Verilog duplicate conditions

Duplicate conditions decrease readability and could lead to unused code. Duplicate conditions are often an unintended result of copy-pasting. Sigasi marks these duplicates as warnings (rule 98).

VERILOG
module bad_code(input clk);
    if(clk && clk) begin
        // Do something
    end
endmodule

VERILOG
module good_code(input clk);
    if(clk) begin
        // Do something
    end
endmodule

This is also the case for if-else chains or switch cases.

VERILOG
module bad_code(input clk);
    if(clk) begin
        // Do something
    end else if(clk) begin
        // Never called
    end

    typedef enum {INIT, IDLE, START, READY} t_state;
    t_state state;

    always @(posedge clk) begin
        case (state)
            IDLE    : state = START;
            IDLE    : state = READY; // Never called
            READY   : state = IDLE ;
        endcase
    end
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.98.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
98/severity/${path}={error|warning|info|ignore}
```