Verilog duplicate continuous assignments

Sigasi warns if a signal is assigned a value in multiple continuous assignments (rule 101). Duplicate continuous assignments are optimized away during synthesis. Having duplicates decreases the readability of the code and may lead to mistakes.

VERILOG
module bad_sumff(input clk, rst_n, logic[31:0] d1, d2, output logic[31:0] q);
    wire logic[31:0] sum = d1 + d2;

    assign sum = d1 + d2;

    always @(posedge clk or negedge rst_n)
    if (~rst_n)
        q <= 32'b0;
    else
        q <= sum;

    assign sum = d1 + d2;
endmodule

VERILOG
module sumff(input clk, rst_n, logic[31:0] d1, d2, output logic[31:0] q);
    wire logic[31:0] sum;

    assign sum = d1 + d2;

    always @(posedge clk or negedge rst_n)
    if (~rst_n)
        q <= 32'b0;
    else
        q <= sum;
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

TEXT

101/severity/${path}={error|warning|info|ignore}