Duplicate signal in sensitivity list

Verilog allows specifying the same signal multiple times in a sensitivity list, but in most cases this is an oversight and the duplicate should be removed.

VERILOG
always @(clk,  clk ,  clk )

VERILOG
always @(edge clk, negedge  clk , posedge  clk )

VERILOG
always @(edge  clk , clk)

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.160.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
160/severity/${path}={error|warning|info|ignore}
```