Duplicate signal in sensitivity list

Verilog allows specifying the same signal multiple times in a sensitivity list, but in most cases this is an oversight and the duplicate should be removed.

always @(clk,  clk ,  clk )

always @(edge clk, negedge  clk , posedge  clk )

always @(edge  clk , clk)

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

160/severity/${path}={error|warning|info|ignore}