A non-blocking assignment (<=) is not allowed in Verilog (2005) functions.
SystemVerilog (2017) does allow non-blocking assignments in functions, but only in specific contexts.
A function with non-blocking assignments can only be called in initial procedures, always procedures, and in a context
where a side effect is allowed. Ensuring these conditions are met is not straightforward.
On top of this, they can make the design harder to understand.
Sigasi flags an error if a non-blocking assignment is used in a Verilog function (rule 41) and can optionally
flag a problem for the same issue in SystemVerilog functions (rule 171, disabled by default).
A good fix to resolve the problem is to replace non-blocking assignments (<=) with blocking assignments (=)
module badcode;
function plus_one;
input integer a;
begin
plus_one <= a + 1; // Incorrect: non-blocking assignment
end
endfunction
endmodule
module goodcode;
function plus_one;
input integer a;
begin
plus_one = a + 1; // Correct: blocking assignment
end
endfunction
endmoduleRule configuration
These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.
For Modular Projects, add these entries to your project's
.sigasi/settings.jsonsettings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an@overrideblock; to scope them to a specific target, place them inside a@targetsblock.JSONC{ "verilog.rules.171.severity": "{ERROR|WARNING|INFO|IGNORE}" // Non-blocking assignments in functions }For Classic Projects, add the VHDL lines to
.settings/com.sigasi.hdt.vhdl.linting.prefsand the Verilog/SystemVerilog lines to.settings/com.sigasi.hdt.verilog.linting.prefs:PREFS171/severity/${path}={error|warning|info|ignore} # Non-blocking assignments in functions