Verilog hiding non-virtual methods

For a class method to override a method, the corresponding method in the superclass must be virtual. If the method in the superclass is not virtual, it will be hidden instead. Hiding methods instead of overriding them is often unintentional and may indicate a missing virtual keyword (rule 132).

VERILOG
class Parent;
    function void f();
        ...
    endfunction

    virtual function void g();
        ...
    endfunction
endclass

class Child extends Parent;
    function void f();
        ...
    endfunction

    function void g();
        ...
    endfunction
endclass

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.132.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
132/severity/${path}={error|warning|info|ignore}
```