Verilog identifiers and data types

VHDL keywords as module name

The use of VHDL keywords as a (System)Verilog module name is not recommended. In mixed-language projects in particular it could lead to unexpected results. Sigasi warns when a VHDL keyword is used as a module name (rule 7).

VERILOG
module entity;
endmodule

module my_module;
endmodule

Underscores in identifier names

The following naming cases should be avoided in Verilog identifiers:

module or port name ending with an underscore: bad_
any name having consecutive underscores: very__bad

The recommendation is mainly based on tool and library compatibility issues. This is a typical unofficial convention to reserve those types of names as internal to tools.

Sigasi warns for consecutive underscores (rule 42) and trailing underscores (rule 43) in module and port names.

VERILOG
module bad__code(input clk_);
endmodule

module goodcode(input clk);
endmodule

Non-packed member in packed struct or union

Packed structures and unions can only contain members of packed data types and integer data types (rule 59).

VERILOG
class AClass; endclass

typedef struct packed { int a;    } intstruct;
typedef struct packed { real a;   } realstruct;
typedef struct packed { AClass a; } classstruct;

Illegal type in untagged union

Dynamic types and chandle types can not be used in untagged unions (rule 60).

VERILOG
class AClass; endclass

typedef union { int a;    } intunion;
typedef union { string a; } stringunion;
typedef union { AClass a; } classunion;

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "verilog.rules.7.severity": "{ERROR|WARNING|INFO|IGNORE}", // VHDL keywords as module name
    "verilog.rules.42.severity": "{ERROR|WARNING|INFO|IGNORE}", // Consecutive underscores
    "verilog.rules.43.severity": "{ERROR|WARNING|INFO|IGNORE}"  // Trailing underscores
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
7/severity/${path}={error|warning|info|ignore} # VHDL keywords as module name
42/severity/${path}={error|warning|info|ignore} # Consecutive underscores
43/severity/${path}={error|warning|info|ignore} # Trailing underscores