Abstract classes cannot be instantiated

In Verilog, abstract (virtual) classes cannot be directly instantiated.

module main_test;
    virtual class A;
        pure virtual function real getData();
    endclass;
    class B extends A;
        virtual function real getData();
            return 3.1415;
        endfunction
    endclass;
    A a;
    initial begin
        a = new;
        a = B::new;
    end
endmodule