Verilog inputs

Although the input direction is taken by default, it is preferable to explicitly specify the direction to improve readability and make the code self-documenting.

VERILOG
module bad_example;

	function int my_func(int a, b);          // bad: direction of a and b omitted
		return a+b;
	endfunction
	
	task my_task(int a, b);                 // bad: direction of a and b omitted
	begin
		$display(a);
		$display(b);
	end
	endtask
	
endmodule

VERILOG
module good_example;

	function int my_func(input int a, b);   // good: direction of a and b specified
		return a+b;
	endfunction
	
	task my_task(input int a, b);          // good: direction of a and b specified
	begin
		$display(a);
		$display(b);
	end
	endtask
	
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:

TEXT

14/severity/${path}={error|warning|info|ignore}