Order of named declaration list does not match

This style validation checks whether the relative order of the port connection, argument, or parameter list matches the order used in the declaration.

Port connections

VERILOG
module top(input a, output b, inout c);
endmodule

module example();
    logic a, b, c;
    top explicit_named_ordered(.a(a), .b(b), .c(c));
    top explicit_named_unordered(.a(a), .c(c), .b(b));

    top implicit_named_ordered(.a, .b, .c);
    top implicit_named_unordered(.a, .c, .b);
endmodule

Arguments

VERILOG
task tsk(input logic a, output b, output c);
endtask : tsk

function func(input logic a, output b, output c);
endfunction : func

class Cls;
    function new(input logic a, output b, output c);
    endfunction
endclass

module test();
    logic a, b, c;
    Cls inst = new(.a(a), .c(c), .b(b));
    initial begin
        tsk(.b(b), .c(c), .a(a));
        func(.a,.b, .c);
    end
endmodule : test

Parameters

VERILOG
module top#(type A, B)();
endmodule

class Cls#(type A, B);
endclass

module test();
    Cls#(.A(logic), .B(5)) inst = new();
    top#(.B(5), .A(logic)) top_instance();
endmodule : test

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "verilog.rules.163.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.163.parameters.check_port_connections": {true|false},
    "verilog.rules.163.parameters.check_arguments": {true|false},
    "verilog.rules.163.parameters.check_parameters": {true|false}
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
163/severity/${path}={error|warning|info|ignore}
163/params/check_port_connections/${path}={true|false}
163/params/check_arguments/${path}={true|false}
163/params/check_parameters/${path}={true|false}