Names differing only by case

Using names that differ only by case is not desirable, even if this is valid in Verilog. This can be confusing, or it may have been a mistake on the part of the original developer.

Avoiding such mistakes improves readability, prevents potential issues, and encourages a good style.

Sigasi can report this as a warning.

VERILOG
class my_class;
    // class definition
endclass

class MY_CLASS;
    // class definition
endclass

VERILOG
module m;
    int abc = 1;
    int Abc = 1;
    int ABC = 1;
    int s = abc + Abc + ABC;
    $display("Sum = %0d", s);
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.166.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
166/severity/${path}={error|warning|info|ignore}
```