Non-standard assignment patterns

Some tools accept assignment patterns without the leading apostrophe ('). This syntax is not LRM compliant and is not portable across simulators.

Sigasi accepts this syntax for compatibility and reports it as a warning (rule 186), so you can migrate to portable syntax.

A Quick Fix to add the missing leading apostrophe is offered for this rule.

VERILOG
module top;
    // Non-standard form (accepted by some tools, rejected by others)
    int priorities_non_standard[string] = {"high": 3, "low": 1};

    // Standard, portable form
    int priorities_standard[string] = '{"high": 3, "low": 1};
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.186.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
186/severity/${path}={error|warning|info|ignore}
```