Non-standard assignment pattern member

An assignment pattern can be the target of an assignment. The SystemVerilog standard requires each member of such a pattern to be bit-stream data, which rules out a real variable. Some tools accept other members as well, but such code is not portable.

Sigasi accepts these members for compatibility and reports them as warnings (rule 187).

VERILOG
module top;
    typedef struct { real r; string s; } pair_t;
    pair_t pair = '{3.14, "pi"};

    real   r;
    string s;

    initial begin
        // Non-standard form (accepted by some tools, rejected by others)
        '{r, s} = pair;

        // Standard, portable form
        r = pair.r;
        s = pair.s;
    end
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.187.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
187/severity/${path}={error|warning|info|ignore}
```