Non-standard covergroup option

Accellera’s SystemVerilog 3.1a extension to the Verilog standard defined the cross_auto_bin_max coverage option for covergroups and crosses to set the maximum number of automatically created cross product bins for a cross. This option, however, did not make it to an IEEE Standard for SystemVerilog, and thus not every EDA tool supports it. Sigasi marks usages of this option as warnings.

covergroup cg(byte a, b);
	cross a, b {
		bins a0_any_b = binsof(a) intersect {0} && binsof(b);
		bins a1_b1    = binsof(a) intersect {1} && binsof(b) intersect {1};
		option.cross_auto_bin_max = 0;
	}
endgroup

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

• Modular Projects
• Classic Projects

• For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

  JSONC

  {
      "verilog.rules.184.severity": "{ERROR|WARNING|INFO|IGNORE}"
  }

• For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

  PREFS

  184/severity/${path}={error|warning|info|ignore}