Non-standard time literal

The SystemVerilog standard only allows integer and fixed-point notation in a time literal, such as 100ms or 0.1s. Some tools also accept scientific notation, such as 100e-3s, but such code is not portable.

Sigasi accepts scientific notation for compatibility and reports it as a warning (rule 188), both in time literals and in delays.

VERILOG
module top;
    // Non-standard form (accepted by some tools, rejected by others)
    time t1 = 100e-3s;
    initial #1e3ns $finish;

    // Standard, portable form
    time t2 = 0.1s;
    time t3 = 100ms;
    initial #1000ns $finish;
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.188.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
188/severity/${path}={error|warning|info|ignore}
```