Some tools permit implicit type conversions that are not specified by the Verilog or SystemVerilog standards. Making use of such non-standard conversions will reduce the portability of the design. Sigasi will mark non-standard implicit conversions as warnings.
Streaming concatenations
The SystemVerilog standard does not allow streaming concatenations to be used as expression operands without an explicit type cast. However, certain tools allow it and will perform an implicit type cast. Sigasi will mark these implicit conversions as warnings (rule 173).
module top;
logic [31:0] a = '0, b = '0;
initial begin
b = 32'h12345678;
a = cond ? {<<4 {b}} : b;
end
endmodule
Integral to enum conversion
Many tools will allow implicit conversions from integral to enum types. Such implicit conversions are not supported by the SystemVerilog standard and will be marked as a warning by Sigasi (rule 176).
module top;
enum {RED, YELLOW, GREEN} light;
initial begin
light = 2;
end
endmodule
Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured with the following template:
173/severity/${path}={error|warning|info|ignore}
176/severity/${path}={error|warning|info|ignore}