Verilog out-of-bound method declarations

An out-of-block method declaration signature should match its prototype declaration’s signature. Sigasi flags an error if the prototype and the implementation signatures have a:

different subroutine form (task or function)
different return type, if it is a function
different arity or any argument has a:
- different name
- different direction
- mismatched type

If an argument default value is present in an out-of-block method declaration but is missing in the prototype, or default values are not syntactically identical, a warning message is reported (rules 90, 91).

Errors are also reported for a missing prototype for out-of-bound definitions and missing or duplicated definitions for an extern method prototype.

VERILOG
class C;
    extern task proto_only();       // missing definition
    extern task who_am_i();
    extern function bit bad(input int a, b, c, d, e = 2 + 3);

    extern function int good(input int a, output string b);
endclass

function C::who_am_i();             // should be a task
    // ...
endfunction

function C::no_proto();             // missing prototype
    // ...
endfunction

function logic C::bad(              // should return bit
    output int a,                   // should be input
    input integer b,                // should be int
    input int si,                   // should be 'c'
    input int d = 4,                // should have no default value
    input int e = 5                 // should be same value as prototype: 2 + 3
);
    // ...
endfunction

function bit C::bad(ref x, y);      // completely different signature, duplicate definition
    // ...
endfunction

function int C::good(input int a, output string b);
    // ...
endfunction

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.90.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.91.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
90/severity/${path}={error|warning|info|ignore}
91/severity/${path}={error|warning|info|ignore}
```