Verilog parameters

Sigasi validates the use of parameters in (System)Verilog.

Parameters without a default value

Sigasi warns if a parameter is declared without a default value (rule 19). Syntactically this is allowed since the instantiating modules should provide the value to the instance parameter. However, it is undesirable since it makes the definition dependent on a particular hierarchy and limits code reusability. In addition, it is creating elaboration errors when attempting to use such modules as a top-level.

VERILOG
module badcode;
	parameter P;
	initial
	    $display(P);
endmodule

module goodcode;
	parameter P = 0;
	initial
	    $display(P);
endmodule

Parameters width mismatch

Sigasi flags an error if a parameter with a defined width is declared is assigned a value of differing width (rule 48).

VERILOG
parameter int         p = 'h764321098;   // Number of bits set a04a (35) wider than the expected bit width (32)

<span class="goodcode">parameter signed [36] q = 'h764321098;

Local parameter has to be initialized

The Verilog standard requires that local parameters are initialized (rule 69).

VERILOG

localparam p;             // initialization missing

localparam p = 1;

Local parameter cannot be overridden

The Verilog standard does not allow the overriding of local parameters (rule 70).

VERILOG
module name(
    input clk,
    input rst
);
    localparam int test = 42;

    defparam test = 0;    // override not allowed
endmodule : name

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

JSONC
{
    "verilog.rules.19.severity": "{ERROR|WARNING|INFO|IGNORE}", // parameter without default value
    "verilog.rules.48.severity": "{ERROR|WARNING|INFO|IGNORE}", // parameter width mismatch
    "verilog.rules.69.severity": "{ERROR|WARNING|INFO|IGNORE}", // local parameter not initialized
    "verilog.rules.70.severity": "{ERROR|WARNING|INFO|IGNORE}"  // local parameter overridden
}

For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

PREFS
19/severity/${path}={error|warning|info|ignore} # parameter without default value
48/severity/${path}={error|warning|info|ignore} # parameter width mismatch
69/severity/${path}={error|warning|info|ignore} # local parameter not initialized
70/severity/${path}={error|warning|info|ignore} # local parameter overridden