Avoid using general purpose 'always'

SystemVerilog has three specific always procedures: always_comb, always_latch and always_ff. These should be used in favor of general purpose always in synthesizable designs because:

they describe the intent of the always procedure
they provide semantics that improve readability
tools can additionally check for correctness concerning their behavior

Sigasi reports generic always procedures as a warning.

VERILOG
module m (input clk);
    always @(clk) begin
    end
endmodule

Sigasi offers Quick Fixes to use a specific always procedure instead.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.170.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
170/severity/${path}={error|warning|info|ignore}
```