Prohibited macro

Some macros might be deprecated, or their use might be discouraged by certain guidelines. This check can be configured with a list of prohibited macros, all uses of these macros will be flagged as a warning.

For example, if the size macro is configured to be prohibited:

VERILOG
// Deprecated
`define size 42

...

module my_module(input logic clk, rst);
   logic [`size : 0] data;
   ...
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.129.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.129.parameters.prohibited_macros": ["${macro}", ...]
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
129/severity/${path}={error|warning|info|ignore}
129/params/prohibited_macros/${path}=[macro...]
```