Verilog reg and logic datatype

In SystemVerilog, the reg datatype is deprecated. It is recommended to use the logic datatype instead.

Sigasi warns when the reg datatype is used in SystemVerilog.

A Quick Fix is available to convert reg into logic.

module my_module;
    reg   deprecated;
    logic good;
endmodule

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

• Modular Projects
• Classic Projects

• For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

  JSONC

  {
      "verilog.rules.3.severity": "{ERROR|WARNING|INFO|IGNORE}"
  }

• For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

  PREFS

  3/severity/${path}={error|warning|info|ignore}