Tool compatibility rules

Different EDA tools have extended the Verilog and SystemVerilog standard in diverging ways. To maximize tool compatibility, Sigasi allows some constructs not included in the standards. The linting rules listed below mark the usage of such constructs as a warning, which can be disabled individually if you use a tool that allows a particular construct.

Whitespace following a backtick

Some tools allow additional whitespace following the backtick of a preprocessor directive.

VERILOG
`define A 1
` define B 2 /* unexpected whitespace following the backtick */

Invalid preprocessor syntax

Some directives and escape sequences such as `` and `" can only be used inside the body of a macro definition. Some tools are however more lenient, allowing them also elsewhere.

VERILOG
var asdf = `"asdf"; // Unexpected `" directive outside macro body

Rule configuration

These rules can be disabled for your project, or their severity and parameters can be modified in the project linting settings. Alternatively, they can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.117.severity": "{ERROR|WARNING|INFO|IGNORE}", // Whitespace following a backtick
    "verilog.rules.121.severity": "{ERROR|WARNING|INFO|IGNORE}"  // Invalid preprocessor syntax
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
117/severity/${path}={error|warning|info|ignore} # Whitespace following a backtick
121/severity/${path}={error|warning|info|ignore} # Invalid preprocessor syntax
```