Some tools allow combinations of unary operators with increment/decrement operators (for example, ~retries++), while others reject this syntax. This combination is not standard-compliant and is not portable across simulators.
Sigasi reports this portability issue as a warning (rule 175).
module test;
int retries = 3;
always begin
if (~retries--) begin
$display("retry");
end else begin
$finish;
end
end
endmoduleTo resolve this issue, add parentheses so the increment/decrement operation is explicitly applied first.
module test;
int retries = 3;
always begin
if (~(retries--)) begin
$display("retry");
end else begin
$finish;
end
end
endmoduleRule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.
For Modular Projects, add these entries to your project's
.sigasi/settings.jsonsettings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an@overrideblock; to scope them to a specific target, place them inside a@targetsblock.JSONC{ "verilog.rules.175.severity": "{ERROR|WARNING|INFO|IGNORE}" }For Classic Projects, add the VHDL lines to
.settings/com.sigasi.hdt.vhdl.linting.prefsand the Verilog/SystemVerilog lines to.settings/com.sigasi.hdt.verilog.linting.prefs:PREFS175/severity/${path}={error|warning|info|ignore}