Unexpected content following directive

Even though the Verilog specification does not allow additional trailing content on lines with preprocessor directives, many tools allow this. The non-standard compliant content is marked with a warning.

VERILOG
`include "warning.svh"; // Trailing content in directive line
`include "ok.svh"
; // Insert a newline after the directive to comply with the specification

It is recommended that you fix these problems since they are not covered by the Verilog standard.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.156.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
156/severity/${path}={error|warning|info|ignore}
```