Incorrect constructor for UVM object or component

UVM objects and components must declare an explicit constructor that follows a certain format:

for UVM objects the first argument of the constructor must be string name, and all arguments must be optional.
for UVM components the first two arguments of the constructor must be string name and uvm_component parent, and all additional arguments must be optional.

VERILOG
class my_uvm_component extends uvm_component;
    `uvm_component_utils(my_uvm_component)

    // The following incorrect constructor will be implied:
    // function new();
    //      super.new();
    // endfunction
endclass

VERILOG
class my_uvm_component extends uvm_component;
    `uvm_component_utils(my_uvm_component)  

    // The constructor does not have the correct arguments
    function new(int parent, string name);
        super.new(name, parent);
    endfunction
endclass

VERILOG
class my_uvm_component extends uvm_component;
    `uvm_component_utils(my_uvm_component)  

    // The additional argument is not optional
    function new(string name, uvm_object parent, int i);
        super.new(name, parent);
    endfunction
endclass

VERILOG
class my_uvm_component extends uvm_component;
    `uvm_component_utils(my_uvm_component)  

    function new(string name, uvm_object parent, int i = 0);
        super.new(name, parent);
    endfunction
endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.154.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
154/severity/${path}={error|warning|info|ignore}
```