Incorrect utility macro

There are multiple variants of the UVM utility macros, each one used to register a different kind of UVM object class:

UVM components must use the component variants, all other UVM objects must use the object variants
Parameterized classes must use the param variants
Virtual classes must use the abstract variants (UVM 2017 or higher)

VERILOG
class my_uvm_component#(type type_param) extends uvm_component;
    `uvm_object_utils(my_uvm_component#(type_param))

    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction
endclass

VERILOG
class my_uvm_component#(type type_param) extends uvm_component;
    `uvm_component_param_utils(my_uvm_component#(type_param))

    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction
endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.146.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
146/severity/${path}={error|warning|info|ignore}
```