Incorrect UVM object instantiation

Using the factory to create UVM objects and components—instead of allocating them directly via new—allows the type of an object to be determined at run time rather than at compile time. Hence it can to be overridden without modifying the requesting class.

Instantiations should take the form:

VERILOG
my_obj = my_type::type_id::create("my_obj");

This increases the reusability of your verification components:

VERILOG
class my_agent extends uvm_agent;
	`uvm_component_utils(my_agent)

	my_sequencer  m_sequencer;
	my_driver     m_driver;
	my_monitor    m_monitor;

	function void build_phase(uvm_phase phase);
		// Incorrect instantiation of UVM object 'my_sequencer', use the factory instead
		m_sequencer = new("m_sequencer", this);
		// Incorrect instantiation of UVM object 'my_driver', use the factory instead
		m_driver    = my_driver::new("m_driver", this);
		m_monitor   = my_monitor::type_id::create("m_monitor", this);
	endfunction

endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.148.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
148/severity/${path}={error|warning|info|ignore}
```