Type argument value does not match containing class

There are several UVM macros for which the first argument must be the equal to containing class. These macros are:

All UVM object and component utility macros
uvm_field_utils_begin
uvm_sequence_library_utils
uvm_add_to_seq_lib
uvm_set_super_type
uvm_register_cb

VERILOG
class my_uvm_component extends uvm_component;

    `uvm_component_utils(some_other_class)

    ...

endclass

VERILOG
class my_uvm_component extends uvm_component;

    `uvm_component_utils(my_uvm_component)

    ...

endclass

If the containing class is parameterized, the parameters must also be passed to the macro:

VERILOG
class my_uvm_component#(int size_param = 8) extends uvm_component;

    `uvm_component_param_utils(my_uvm_component)

    ...

endclass

VERILOG
class my_uvm_component#(int size_param = 8) extends uvm_component;

    `uvm_component_param_utils(my_uvm_component#(size_param))

    ...

endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.147.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
147/severity/${path}={error|warning|info|ignore}
```