Unexpected output system task

Reporting in UVM classes should always be done with one of the eight standard reporting macros, `uvm_info, `uvm_info_context, and so forth, rather than ad hoc $display statements or similar. Simulation run time can be dominated by I/O operations, so it is important to use the reporting features of UVM, such as message verbosity, to control the number of messages being generated.

VERILOG
class my_driver extends uvm_driver#(my_item);
	`uvm_component_utils(my_driver)

	task read(my_item req);
		// ...
		// Unexpected invocation of '$display', use UVM reporting macros instead
		$display("read: %s", req.convert2string());
	endtask

	task write(my_item req);
		// ...
		`uvm_info("write", req.convert2string(), UVM_HIGH)
	endtask
endclass

This rule can be configured to report file output system tasks ($fdisplay, $fwrite, …) too:

VERILOG
class my_test extends uvm_test;
  `uvm_component_utils(my_test)

  task run_phase(uvm_phase phase);
    int fd = $fopen("my_test.log", "w");
    repeat (1000) begin
      my_instr instr = my_instr::generate_random();
      // ...
      // Unexpected invocation of '$fwrite', use UVM reporting macros instead
      $fwrite(fd, {instr.convert2string(),"\n"});
    end
    $fclose(fd);
  endtask
endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.150.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.150.parameters.report_file_output_system_tasks": {true|false}
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
150/severity/${path}={error|warning|info|ignore}
150/params/report_file_output_system_tasks/${path}={true|false}
```