Unregistered UVM object

UVM objects and components must be registered with the factory using one of the UVM utility macros.

VERILOG
class my_uvm_component extends uvm_component;
    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction
endclass

VERILOG
class my_uvm_component extends uvm_component;

    `uvm_component_utils(my_uvm_component)

    function new(string name, uvm_component parent);
        super.new(name, parent);
    endfunction
endclass

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.145.severity": "{ERROR|WARNING|INFO|IGNORE}",
    "verilog.rules.145.parameters.allow_unregistered_virtual_uvm_objects": {true|false}
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
145/severity/${path}={error|warning|info|ignore}
145/params/allow_unregistered_virtual_uvm_objects/${path}={true|false}
```