Implicit vector to boolean conversion

When a vector signal is used as a conditional expression or as an argument to logical operators (e.g. &&, ||, !) it’s implicitly converted to scalar value 0 (false) if all vector bits are zero or to 1 (true) otherwise. It’s not clear in this case if such conversion was intentional or by mistake, and a scalar type or bitwise operator, such as &, |, or ~ was expected.

VERILOG
module ff(input clk, [7:0] d, rst, output [7:0] q);
    always_ff @(posedge clk) begin
        if (rst)                   // Implicit conversion of 'logic [7:0]' to boolean
            q <= 0;
        else
            q <= !d;               // Implicit conversion of 'logic [7:0]' to boolean
    end
endmodule

It may be better to explicitly compare the vector with zero (vec == 0 or vec != 0) if that’s your intent.

Note that this rule is disabled (set to IGNORE) by default.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.
JSONC
```
{
    "verilog.rules.144.severity": "{ERROR|WARNING|INFO|IGNORE}"
}
```
For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:
PREFS
```
144/severity/${path}={error|warning|info|ignore}
```