None or multiple matching entities for component

Each VHDL component must be matched with a corresponding entity, either based on its name and interface or through a configuration. When Sigasi encounters a component that cannot be linked to any entity or a component that is linked to multiple entities, an issue is reported.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

• Modular Projects
• Classic Projects

• For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

  JSONC

  {
      "vhdl.rules.90.severity": "{ERROR|WARNING|INFO|IGNORE}"
  }

• For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

  PREFS

  90/severity/${path}={error|warning|info|ignore}