Capitalization of identifiers

Although VHDL is not case-sensitive, it is recommended to always use the same capitalization when referring to the same declaration. Sigasi warns when the capitalization of a reference differs from the capitalization of the declaration. Because external libraries can have different code styles, this linting only checks references in the same library as its declaration.

Capitalization can easily be fixed with a Quick Fix. All capitalization issues in a file can be fixed in one click.

Rule configuration

This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.

• Modular Projects
• Classic Projects

• For Modular Projects, add these entries to your project's .sigasi/settings.json settings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an @override block; to scope them to a specific target, place them inside a @targets block.

  JSONC

  {
      "vhdl.rules.163.severity": "{ERROR|WARNING|INFO|IGNORE}"
  }

• For Classic Projects, add the VHDL lines to .settings/com.sigasi.hdt.vhdl.linting.prefs and the Verilog/SystemVerilog lines to .settings/com.sigasi.hdt.verilog.linting.prefs:

  PREFS

  163/severity/${path}={error|warning|info|ignore}