Deeply nested conditional and loop statements reduce code readability. Restructuring code or extracting logic to functions can help to keep code in a maintainable state.
Another problem is that deep nesting can result in complicated prioritized logic being synthesized increasing circuit size significantly.
Sigasi can report deeply nested sequential loops and conditions. Note that this rule has the maximum nested depth set to 5 and is ignored by default. You can enable it in the VHDL Errors/Warnings settings page ().
Example with a nesting limit of 2:
procedure nested(a : natural) is
begin
if a >= 1 then -- nesting depth 0
if a < 42 then -- nesting depth 1
for I in 0 to 1 loop -- nesting depth 2
case a is -- Statement exceeds conditional and loop nesting limit of 2
when 21 => report integer'image(a) severity note;
when others => null;
end case;
end loop;
end if;
end if;
end procedure nested;Rule configuration
This rule can be disabled for your project, or its severity and parameters can be modified in the project linting settings. Alternatively, it can be manually configured using one of the following templates, depending on the type of project you use.
For Modular Projects, add these entries to your project's
.sigasi/settings.jsonsettings file. To scope the settings to a specific folder or file instead of the whole project, place them inside an@overrideblock; to scope them to a specific target, place them inside a@targetsblock.JSONC{ "vhdl.rules.239.severity": "{ERROR|WARNING|INFO|IGNORE}", "vhdl.rules.239.parameters.limit": ${integer} // at least 1 }For Classic Projects, add the VHDL lines to
.settings/com.sigasi.hdt.vhdl.linting.prefsand the Verilog/SystemVerilog lines to.settings/com.sigasi.hdt.verilog.linting.prefs:PREFS239/severity/${path}={error|warning|info|ignore} 239/params/limit/${path}=${integer} # at least 1